Senior Cyber FPGA Design Verification Engineer, Secret Security Clearance Required

Senior Cyber FPGA Design Verification Engineer, Secret Security Clearance Required, Dedham, MA

We are currently looking for a Senior Cyber FPGA Design Verification Engineer for a great opportunity Dedham, MA. You will be a member of a cross-functional team responsible for product design from system architecture and requirements allocation through product release and production of cost-sensitive secure products. An active Secret security clearance is required for this position. This position is 100% onsite and not open for remote or hybrid.

Senior Cyber FPGA Design Verification Engineer Qualifications:

– Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master’s degree plus a minimum of 6 years of relevant experience.
– Experience with OVM/UVM design verification methodology: bash/csh, Perl, TCL, Python or similar scripting languages; VHDL or similar hardware description languages.
– Experience defining verification methodology for complex FPGAs.
– Ability to analyze requirements, create test plans, build and set up scalable simulation environments from the ground up using SystemVerilog/UVM.
– Familiarity with testing complex designs, code coverage, functional coverage, assertions.
– Ability to work in a dynamic environment that includes working with changing needs and requirements.
– FPGA/ASIC design experience is a plus.
– Familiarity with Xilinx FPGA & Questa Advanced Functional Verification tools is a plus.
– Team player who thrives in collaborative environments and revels in team success.

Benefits include 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more.

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