Digital Design Engineer

Job Description:

• Expert-level Physical Design Knowledge: Proven experience in physical design methodologies including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (DRC/LVS/ERC).

• PnR Ownership: Demonstrated ability to take full ownership of multiple PnR blocks or partitions, driving them from initial netlist to tape-out quality, including timing closure, power optimization, and area efficiency.
• Tape-Out Experience: Strong track record of delivering high-quality designs to tape-out, with deep understanding of signoff flows and tools (e.g., PrimeTime, RedHawk, Calibre).
• Tool Proficiency: Hands-on expertise with industry-standard EDA tools such as Synopsys ICC2/Fusion Compiler, Cadence Innovus, and Mentor Calibre.
• Timing Closure Expertise: Deep understanding of STA, ECO flows, and timing constraints; ability to drive timing closure across complex hierarchical designs.
• Power and Performance Optimization: Experience with power analysis and reduction techniques (e.g., multi-Vt, clock gating, power domains), and performance tuning.
• Cross-functional Collaboration: Ability to work closely with RTL designers, verification engineers, and package/board teams to resolve design and integration issues.
• Leadership and Mentorship: Experience guiding junior engineers, reviewing design work, and setting technical direction for physical design projects.
• Scripting and Automation: Proficiency in scripting languages (TCL, Python, Perl) to automate design flows and improve efficiency.
• Knowledge of Advanced Nodes: Familiarity with challenges and solutions in advanced process nodes (e.g., 5nm, 3nm), including EM/IR, reliability, and manufacturability concerns.

Education:

• Bachelor's degree in Computer Science, Electrical Engineering or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.

Skills:

• Digital VLSI Design ASIC Flow: RTL Design- Simulations, Static Timing Analysis (STA), Timing Constraints and Timing Closure, Universal Verification methodology (UVM), Functional Verification, Functional Coverage, SystemVerilog Assertions, CAD, Clock Domain Crossing, Clock gating; Clock-Tree Synthesis, Low power design, Power Optimization, Skew Implementation, Place & Route (P&R) Implementation, Low Voltage Control, Synthesis, Physical Design, HSpice, Design of CMOS Transistors, SoC Development/Verification, EDA, Transistor Level Design, ATPG, Memory BIST, Logic BIST, Boundary Scan, Scan Insertion, Design for Test (DFT), Floor Planning, Library Design, Layout Design, FPGA, CPU Architecture , Circuit Design,
• Bus Architecture/Protocols: AMBA-APB/AHB, AXI, I2C, SPI, PCI, USB. (1 year) Additional Information Design Tools: Cadence NCVerilog, Synopsys VCS, PrimeTime, Altera Quartus II, Xilinx ISE, Modelsim, Cadence Virtuoso CAD, GTK Wave, dc_shell, Matlab, Labview, FPGA, Layout Automation, Oscilloscopes, Logic Analyzers. Programming Languages: C/C++, Verilog HDL, SystemVerilog;
• Scripting Languages: Perl/ Tcl, UNIX Shell - Bash.